The Atmel AVR instruction set is the machine language for the Atmel AVR, a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage. The instruction set has the following features:
Arithmetic operations work on registers R0-R31 but not directly on RAM and take one clock cycle, except for multiplication and word-wide addition (ADIW and SBIW) which take two cycles.
RAM and I/O space can be accessed only by copying to or from registers. Indirect access (including optional postincrement, predecrement or constant displacement) is possible through registers X, Y, and Z. All accesses to RAM takes two clock cycles. Moving between registers and I/O is one cycle. Moving eight or sixteen bit data between registers or constant to register is also one cycle. Reading program memory (LPM) takes three cycles.
There are two types of conditional branches: jumps to address and skips. Conditional branches (BRxx) can test an ALU flag and jump to specified address. Skips (SBxx) test an arbitrary bit in a register or I/O and skip the next instruction if the test was true.
| Arithmetic | Bit & Others | Transfer | Jump | Branch | Call |
|---|---|---|---|---|---|
|
ADD Rd, Rr COM Rd MUL Rd, Rr |
BSET s |
MOV Rd, Rr |
RJMP K12 |
CPSE Rd, Rr |
RCALL K12 |
Not all instructions are implemented in all AVR controllers. This is the case of the instructions performing multiplications, extended loads/jumps/calls, long jumps, and power control.
| Family | Members | Arithmetic | Branches | Transfers | Bit-Wise |
|---|---|---|---|---|---|
| Minimal Core | AT90S1200 ATtiny11 ATtiny12 ATtiny15 ATtiny28 |
ADD ADC SUB SUBI SBC SBCI AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER |
RJMP RCALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID |
LD ST MOV LDI IN OUT LPM (not in AT90S1200) |
SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR |
| Classic Core up to 8K Program Space | AT90S2313 AT90S2323 ATtiny22 AT90S2333 AT90S2343 AT90S4414 AT90S4433 AT90S4434 AT90S8515 AT90C8534 AT90S8535 ATtiny26 ATmega8515 |
new instructions: ADIW SBIW |
new instructions: IJMP ICALL |
new instructions: LD (now 9 modes) LDD LDS ST (9 modes) STD STS PUSH POP |
(nothing new) |
| Classic Core with up to 128K | ATmega103 ATmega603 AT43USB320 AT76C711 |
(nothing new) | new instructions: JMP CALL |
new instructions: ELPM |
(nothing new) |
| Enhanced Core with up to 8K | ATmega8 ATmega83 ATmega85 |
new instructions: MUL MULS MULSU FMUL FMULS FMULSU |
(nothing new) | new instructions: MOVW LPM (3 modes) SPM |
(nothing new) |
| Enhanced Core with up to 128K | ATmega16 ATmega161 ATmega163 ATmega32 ATmega323 ATmega64 ATmega128 AT43USB355 AT94 (FPSLIC) AT90CAN series AT90PWM series ATmega48 ATmega88 ATmega168 ATmega162 ATtiny13 ATtiny25 ATtiny45 ATtiny85 ATtiny2313 ATmega164 ATmega324 ATmega328 ATmega644 ATmega165 ATmega169 ATmega325 ATmega3250 ATmega645 ATmega6450 ATmega406 |
(nothing new) | (nothing new) | (nothing new) | new instructions: BREAK |
| Enhanced Core with up to 4M | ATmega640 ATmega1280 ATmega1281 ATmega2560 ATmega2561 |
(nothing new) | new instructions: EIJMP EICALL |
(nothing new) | (nothing new) |
| XMEGA core | ATxmega series | new instructions: DES |
(nothing new) | (nothing new) | (nothing new) |
| Reduced Core | ATtiny10 ATtiny9 ATtiny5 ATtiny4 |
(Identical to minimal core, except for reduced CPU register set) | (Identical to classic core with up to 8K, except for reduced CPU register set) | Identical to classic core with up to 8K, with the following exceptions: LPM (removed) LDD (removed) STD (removed) LD (also accesses program memory) LDS (different bit pattern) STS (different bit pattern) Reduced CPU register set |
(Identical to enhanced core with up to 128K, except for reduced CPU register set) |